00: Divide Fault
The processor returns this exeption when it enconters a divide fault. A divide fault occurs if division by zero is attempted or the result of the operation does not fit in the destination operand.
02: NMI Interrupt
Interrupt 02 is reserved for the hardware Non-Maskable-Interrupt condition. Noexeptions trap through interrupt 02
04: Overflow Trap
An overflow trap occurs after an INTO instruction has executed and the 0F bit is set to 1.
05: Bounds Check Fault
The BOUND instruction compares the array index with an upper and lower bound. If the index is out of range, thenthe processor traps to interrupt 05.
06: Invalid Opcode Fault
This error is returned when the processor tries to decode a bit pattern that does not respond to any legal computer instruction. It can also happen when the processor tries to execute an instruction that conains invalid operands. Another senario for this error is when the processor attemps to execute a protected-mode instruction while runnig in virtual 8086 mode. The last posibility for this code being returned is when the processor tries to execute a LOCK prefix with an instruction that cannot be locked.
07: Coprocessor Not Available Fault
This error occurs if the computer does not have a math coprocessor and the EM bit of register CR0 is set indicating the Numeric Data Processor emulation is being used. Each time a floating point operation is executed, an interrupt 07 occurs.
This erros also occurs when a math coprocessor is used and a task swicth is executed. Interrupt 07 tells the processor that the current state of the coprocessor needs to be saved so that it can be used for another task.
08: Double Fault
Processing an exeption sometimes triggers a second exeption. In the event that this occurs, the processor will issue an interrupt 08 for a double fault.
09: Coprocessor Segment Overrun
This error occurs when a floating point causes a memory access that runs beyond the end of the segment. If the starting address of the floating point operand is outside the segment, then a General Protection Fault (GPF) occurs (interrupt 0D).
10 (0Ah): Invalid Task State Segment Fault
Because the Task State Secment contains a number of descriptors, any number of conditions can cause exeption 0A. Typically, the processor can gather enogh information from the Task State Secment to issue another fault pointing to the acual problem.
11 (0Bh): Not Present Fault
The not present interrupt allows the operating system to implement virtual memory through the segmentation mechanism. When a segment is marked as "not present", the segment is swapped out to the disk. The interrupt 0B fault is triggered when the application needs to access the segment.
12 (0Ch): Stack Fault
A stack fault occurs with the error code 0 if an instruction refers to memory beyond the limit of the stack segment. If the operating system supports expand-down segment, increasing the size of the stack should alleviate the problem. Loading the stack secment with invalid descriptors will result in a General Protection Fault (GPF).
13 (0Dh): Genral Protection Fault (GPF)
Any condition not covered by any of the other processor exeptions will result in a GPF. Theexeption indicates the this program has been corrupted in memory, usually resulting in the termination of the program.
14 (0Eh): Page Fault
The page fault interrupt allows the operating system to implement vitual memory on a demand-paged basis. An interrupt 14 usually is based when an access to a page directory entry or page table with the present bit set to 0 (not present) occurs. The operating system makes the page present (usually retrieves the page from virtual memory) and re-issues the faulting instruction, which then can access the segment. A page fault also accurs when a paging protection rule is violated (when the retrieve fails, or data retrieved is invalid, or the code that issued the fault broke the protection rule for the processor). In these cases the operating system takes over for the appropriate action.
16 (10h): Coprocessor Error Fault
This interrupt occurs when an unmasked floating point exeption has signaled a previous instruction. This is because the 80386 does not have access to the floating point unit, it checks the ERROR\ pin to test this condition. This is also triggered by a WAIT instruction if the Emulate Math Coprocessor bit at CR0 is set.
17 (11h): Alignment Check Fault
This interrupt is only used on the 80486 CPU's. An interrupt of 17 is issued when code executing at ring privilege 3 attempts to access a word operand that is not on an even-address bountry, a double-word operand that is not divisible by four, or a long real or temp real address that is not divisible by eight. Alignment checking is disabled when the CPU is first powered up and is only enabled in protect mode.
This information was acquired from Microsoft Support Articles. For more on this subject visit www.microsoft.com
